This relates generally to the field of integrated circuit manufacturing and, more particularly, relates to ferroelectric RAM.
Ferroelectric memory and other types of semiconductor memory are used for storing data and/or program code in personal computer systems, embedded processor-based systems, and the like. Ferroelectric memories are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations, in which data is read from or written to the device using address signals and various other control signals. The individual memory cells typically comprise one or more ferroelectric (FE) capacitors adapted to store a binary data bit, as well as one or more access transistors, typically MOS devices, operable to selectively connect the FE capacitor to one of a pair of complementary bit lines, with the second bit line being connected to a reference voltage. The individual cells are commonly organized as individual bits of a corresponding data word, wherein the cells of a given word are accessed concurrently through activation of plate lines and word lines by address decoding circuitry.
Ferroelectric memory devices provide non-volatile data storage. Ferroelectric memory cells include capacitors constructed with ferroelectric dielectric material that may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within the dielectric material. This alignment may be selectively achieved by application of an electric field to the ferroelectric capacitor in excess of the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles. The response of the polarization of a ferroelectric capacitor to the applied voltage may be plotted as a hysteresis curve.
As illustrated in prior art FIG. 1, a 1T/1C FeRAM cell 10 includes one transistor 12 and one ferroelectric storage capacitor 14. A bottom electrode of the storage capacitor 14 is connected to a drain terminal 15 of the transistor 12. The 1T/1C cell 10 is read by applying a signal to the gate 16 of the transistor (word line WL, e.g., the Y signal), thereby connecting the bottom electrode of the capacitor 14 to the bit line 18 (BL). A pulse signal is then applied to the top electrode contact (the plate line or drive line DL) 20. The potential on the bit line 18 of the transistor 12 is, therefore, the capacitor charge divided by the bit line capacitance. Since the capacitor charge is dependent upon the bi-stable polarization state of the ferroelectric material, the bit line potential can have two distinct values. A sense amplifier (not shown) is connected to the bit line 18 and detects the voltage associated with a logic value of either 1 or 0. Frequently the sense amplifier reference voltage is a ferroelectric or non-ferroelectric capacitor connected to another bit line that is not being read. In this manner, the memory cell data is retrieved.
A characteristic of the illustrated ferroelectric memory cell is that, if the polarization of the ferroelectric is switched, the read operation is destructive and the sense amplifier must rewrite (onto that cell) the correct polarization value after the cell is read. This is similar to the operation of a DRAM. One difference from a DRAM is that a ferroelectric memory cell will retain its state until it is interrogated, thereby eliminating the need of refresh.
As illustrated in prior art FIG. 2, a 2T/2C memory cell 30 couples to a bit line 32 and an inverse of the bit line (“bit line-bar”) 34 that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The dual capacitor ferroelectric memory cell comprises two transistors 36 and 38 and two ferroelectric capacitors 40 and 42, respectively. The first transistor 36 couples between the bit line 32 and a first capacitor 40, and the second transistor 38 couples between the bit line-bar 34 and the second capacitor 42. The first and second capacitors 40 and 42 have a common terminal or plate (the drive line DL) 44 to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors 36 and 38 of the dual capacitor ferroelectric memory cell 30 are enabled (e.g., via their respective word line 46) to couple the capacitors 40 and 42 to the complementary logic levels on the bit line 32 and the bit line-bar line 34 corresponding to a logic state to be stored in memory. The common terminal 44 of the capacitors is pulsed during a write operation to polarize the dual capacitor memory cell 30 to one of the two logic states.
In a read operation, the first and second transistors 36 and 38 of the dual capacitor memory cell 30 are enabled via the word line 46 to couple the information stored on the first and second capacitors 40 and 42 to the bit line 32 and the bit line-bar line 34, respectively. A differential signal (not shown) is thus generated across the bit line 32 and the bit line-bar line 34 by the dual capacitor memory cell 30. The differential signal is sensed by a sense amplifier (not shown) that provides a signal corresponding to the logic level stored in memory.
There are several techniques to interrogate a FeRAM cell. The two most common interrogation techniques are step sensing and pulse sensing. In both these interrogation techniques, the cell capacitor is coupled to the complementary bit line by turning ON an access or a pass gate. In step sensing, the plate line voltage is stepped from ground (Vss) to a supply voltage (Vdd). In pulse sensing, the plate line voltage is pulsed from Vss to Vdd and then back to Vss. This provides a differential voltage on the bit line pair, which is connected to a sense amp circuit. The reference voltage is typically supplied at an intermediate voltage between a voltage (V“0”) associated with a capacitor programmed to a binary “0” and that of the capacitor programmed to a binary “1” (V“1”). The resulting differential voltage at the sense amp terminals represents the data stored in the cell, which is buffered and applied to a pair of local I/O lines.
The transfer of data between the ferroelectric memory cell, the sense amp circuit, and the local data bit lines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry in the device. In a typical ferroelectric memory read sequence, two sense amp bit lines are initially pre-charged to ground, and then floated, after which a target ferroelectric memory cell is connected to one of the sense amp bit lines and interrogated. Thereafter, a reference voltage is connected to the remaining sense amp bit line, and a sense amp senses the differential voltage across the bit lines and latches a voltage indicative of whether the target cell was programmed to a binary “0” or to a “1”.
In modern memory devices having millions of data cells, there is a continuing need to reduce component sizes and otherwise to conserve circuit area in the device, so as to maximize device density.